The present invention relates to semiconductor devices, and more particularly, to nanowire field effect transistor (FET) devices.
A field-effect transistor (FET) includes a source region, a drain region and a channel between the source and drain regions. A gate is formed over the channel and regulates electron flow through the channel between the source and drain regions. Recent trends to reduce the size of FET devices have led to the development of gate-all-around nanowire channel field effect transistors (e.g., nanowire FETs). Nanowire FETs are expected to enable density scaling beyond current planar CMOS technology due to their superior electrostatic characteristics. There are, however, notable challenges related to fabricating gate-all-around nanowire FETs, especially at scaled dimensions. For instance, to increase layout density, the nanowires are placed close together and/or are stacked. Consequently, forming a gate surrounding the nanowires in this case is challenging.
When forming a nanowire FET, typical fabrication methods include first forming a semiconductor fin on an upper surface of a substrate, and subsequently etching a bottom portion of the fin to form a void that defines the semiconductor nanowire. In this manner, a gate electrode fills the void and wraps around all sides of the nanowire to form a gate-all-around nanowire FET. However, removal of the bottom portion reduces the overall dimensions of semiconductor material, which in turn decreases the current density provided by the nanowire.